`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/03/04 22:06:10
// Design Name: 
// Module Name: Xczu47dr_Top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Xczu47dr_Top(
    input           clk_300m_p,
    input           clk_300m_n,

    input           sdo_u24,
    output          sdi_u24,
    output          sclk_u24,
    output          cs_u24,

    input           sdo_u26,
    output          sdi_u26,
    output          sclk_u26,
    output          cs_u26,

    output          CLKuWire,
    output          DATAuWire,
    output          LEuWire
    );

wire clk;
wire clk_100m;
wire rst;
assign rst = 1'b0;
reg rst_self = 1'b1;
wire mmcm_locked;
reg [10:0] count_rst = 11'd0;
// wire flag_done;
wire spi_suc_1st;
wire spi_suc_2st;

clk_core clk_core
(
    // Clock out ports
    .clk_out1(clk),     // output clk_out1
    .clk_out2(clk_100m),     // output clk_out2
    // Status and control signals
    .locked(mmcm_locked),       // output locked
   // Clock in ports
    .clk_in1_p(clk_300m_p),    // input clk_in1_p
    .clk_in1_n(clk_300m_n)    // input clk_in1_n
);
always @(posedge clk) 
begin
    if (mmcm_locked) 
    begin
        count_rst <= count_rst == 11'd1000 ? count_rst : count_rst + 1'b1;
    end
    if(count_rst == 11'd1000)
    begin
        rst_self <= 1'b0;
    end
    else
    begin
        rst_self <= rst_self;
    end
end

lmk01010_configure lmk01010_configure(
    .clk(clk),
    .rst(rst_self),
    .sdo(DATAuWire),
    // .flag_done(flag_done),
    .sclk(CLKuWire),
    .csb_n(LEuWire)

    );

EVM_SPI_W EVM_SPI_W(
    .clk                 (clk           ),
    .rst                 (rst_self      ),
    // .flag_done           (flag_done     ), 
    .wirte_suc_flag_1st  (spi_suc_1st   ),
    .wirte_suc_flag_2st  (spi_suc_2st   ),
    .sclk_lmk_u24        (sclk_u24      ),
    .sclk_lmk_u26        (sclk_u26      ),
    .sdi_lmk_u24         (sdi_u24       ),
    .sdi_lmk_u26         (sdi_u26       ),
    .lmk_cs_u24          (cs_u24        ),
    .lmk_cs_u26          (cs_u26        )
    );

ila_clock ila_clock (
	.clk(clk), // input wire clk


	.probe0(spi_suc_1st), // input wire [0:0]  probe0  
	.probe1(spi_suc_2st), // input wire [0:0]  probe1 
	.probe2(rst_self) // input wire [0:0]  probe2
);


endmodule
